1. Field of the Invention
The present invention relates to an internal circuit structure of a semiconductor chip and a method of fabricating the internal circuit structure, and more particularly to an internal circuit structure of a wire-bonding package of a semiconductor chip with bonding pads arranged in an array, such as a ball grid array structure or flip chip structure.
2. Description of the Related Art
As semiconductor technique rapidly improves, the operational speed and the complexity of the semiconductor chips have increased. Accordingly, research in packaging technology comes hereafter for the requirement of higher packaging efficiency. In a wire-bonding package of a semiconductor chip, arrangement of bonding pads on the semiconductor chip is particularly emphasized. Conductive traces on the substrate of the package, such as a ball-grid array (BGA) package, can be lithographically defined to achieve a very fine pitch.
IC bonding pad designs include single in-line bonding pad design, staggered bonding pad design, and array-type bonding pad design. It is desired to increase the maximum allowable pad number that can be designed on a chip with functional consideration, so single in-line bonding pad design is not preferred. Alternatively, the staggered bonding pad design and the array-type bonding pad design relatively increase the maximum allowable pad number and has been used widely in general.
FIG. 1a and FIG. 1b show a staggered BGA package 100. The package 100 has a chip 110 with a staggered bonding pad design (that is, two-tier type arrangement) disposed on the upper surface of a substrate as shown in FIG. 1a, and the surface of the chip 110 is provided with a plurality of the bonding pads 120 positioned in an outer row 121 and an inner row 122, as shown in FIG. 1b. Further, the upper surface of the substrate is provided with a ground ring 130, a power ring 140, and a plurality of conductive traces 160. The bonding pads 120 on the chip 110 include power pads for supplying the source voltage, ground pads for supplying the ground potential, and signal pads (I/O pads), which are respectively connected to the ground ring 130, the power ring 140 and the conductive traces 160 by bonding wires 121a, 121b, 122a and 122b. 
Further, the package of a semiconductor chip with array-type bonding pads is disclosed in Taiwan patent application No. 90125929 xe2x80x9cPACKAGE OF SEMICONDUCTOR CHIP WITH ARRAY-TYPE BONDING PADSxe2x80x9d. FIG. 2a and FIG. 2b show a package 1 of the semiconductor chip with array-type bonding pads. The package 1 has a semiconductor chip 10, in which bonding pads 20 are positioned in at least four rows (four rows exactly in FIG. 2a and FIG. 2b) along each side of the chip 10. The four rows of the bonding pads 20 have an inner row 24, a mid-inner row 23, a mid-outer row 22, and an outer row 21, as shown in FIG. 2b. Further, the inner row 24 and the mid-inner row 23 of the bonding pads 20 serve as signal pads only, and the outer row 21 and the mid-outer row 22 of the bonding pads 20 serve as power pads and ground pads only. The inner row 24 and the mid-inner row 23 of the bonding pads 20 (that is, the signal pads) are disposed in an arrangement similar to the staggered bonding pad design; that is, the inner row 24 and the mid-inner row 23 of the bonding pads 20 are positioned in an interlaced arrangement in relation to an edge of the chip 10. Meanwhile, the mid-outer row 22 of the bonding pads 20 are positioned to align to the inner row 24 of the bonding pads 20 in a perpendicular direction to the edge of the chip 10, and the outer row 21 of the bonding pads 20 are positioned to align to the mid-inner row 23 of the bonding pads 20 in a perpendicular direction to the edge of the chip 10. The bonding pads 20 are connected to the corresponding ground ring 30, power ring 40 and conductive traces 60 by the first, second, third and fourth bonding wires 21a, 22a, 23a and 24a with different loop height.
The package of the semiconductor chip with array-type bonding pads has a larger maximum allowable pad number that can be designed on the chip than the staggered BGA package. That is, with the array-type bonding pad design, the chip size can be reduced with the same number of bonding pads provided on the chip, so as to reduce cost and increase package quality of the chip.
However, with the array-type bonding pad design, the internal circuit of the chip is limited in a more restricted area, which leads to problem in the internal circuit arrangement.
FIG. 3 shows an example of the internal circuit structure of the staggered chip 110. In FIG. 3, the outer row 121 of the bonding pads 120 are power pads or ground pads, which are electrically connected to the power/ground circuit macros 180 by first signal lines, in which the first signal lines are formed with power/ground buses 128. Meanwhile, the inner row 122 of the bonding pads 120 are signal pads (I/O pads), which are electrically connected to the signal circuit macros 170 by second signal lines, in which the second signal lines are formed with signal buses 126. Each of the signal circuit macros 170 and the power/ground circuit macros 180 are positioned to align the corresponding bonding pads 120 and adjacent to each other, in which a circuit macro has a width W substantially equal to the bonding pad pitch P.
In the staggered semiconductor chip, each of the signal circuit macros 170 and the power/ground circuit macros 180 are positioned to align the corresponding bonding pads 120 and adjacent to each other. However, in the semiconductor chip with array-type bonding pads, the mid-outer row 22 of the bonding pads 20 are positioned to align to the inner row 24 of the bonding pads 20 in a perpendicular direction to the edge of the chip 10, and the outer row 21 of the bonding pads 20 are positioned to align to the mid-inner row 23 of the bonding pads 20 in a perpendicular direction to the edge of the chip 10. Thus, if the internal circuit of the semiconductor chip with array-type bonding pads is arranged as the aforementioned internal circuit arrangement of the staggered semiconductor chip, the circuit macros may interfere each other, so that the internal circuit structure can not function regularly.
In view of this, the present invention relates to a internal circuit structure of a semiconductor chip with array-type bonding pads, which provides a corresponding internal circuit structure while increasing the maximum allowable pad number that can be designed on the chip. That is, the present invention discloses an internal circuit structure for the semiconductor chip with array-type bonding pads, so that the semiconductor chip with array-type bonding pads can be practically achieved. Thus, the chip size can be reduced with the same number of bonding pads provided on the chip, so as to reduce cost and increase package quality of the chip.
The present invention discloses a semiconductor chip, which has a plurality of bonding pads located about periphery of the semiconductor chip, a plurality of signal circuit macros being positioned inside the bonding pads of the semiconductor chip, and an electro-static discharge clamping circuit ring being positioned between the signal circuit macros and the inner row of the bonding pads. The bonding pads are positioned in at least four rows along each side of the semiconductor chip, in which the four rows has an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads. Further, each of the signal circuit macros is positioned to align to the corresponding bonding pads.
Further, the present invention discloses a method of fabricating a semiconductor chip, comprising the steps of: providing a substrate with a plurality of signal circuit macros and a electro-static discharge clamping circuit ring formed with power/ground circuit, wherein the signal circuit macros and the electro-static discharge clamping circuit ring are insulated to each other; forming a plurality of conductive layers sequentially above part of the substrate, wherein insulating layers are formed between the conductive layers; forming a plurality of bonding pads on part of the conductive layers, wherein the bonding pads are positioned in at least four rows, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row; and forming a plurality of vias in the insulating layers, wherein the outer row and the mid-outer row of the bonding pads is connected to a predetermined portion of the conductive layers above the signal circuit macros by the conductive layers and the electro-static discharge clamping circuit ring to form a first signal line, the inner row and the mid-inner row of the bonding pads is connected to the signal circuit macros by the conductive layers to form a second signal line, and the first signal line and the second signal line are insulated to each other.
In the present invention, it is preferable that the inner row and the mid-inner row of the bonding pads are positioned in an interlaced arrangement in relation to an edge of the chip, the mid-outer row of the bonding pads are positioned to align to the inner row of the bonding pads in a perpendicular direction to the edge of the chip, and the outer row of the bonding pads are positioned to align to the mid-inner row of the bonding pads in a perpendicular direction to the edge of the chip. Further, each of the signal circuit macros preferably has a width substantially equal to a bonding pad pitch. Further, a power/ground circuit ring can be provided above the signal circuits to supply power to the signal circuit macros.
The semiconductor chip of the present invention is suited to a flip chip structure or a ball grid array (BGA) package.